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Debugging over USB

USB_Übersicht
OVERVIEW

Full Debug and Trace Experience via USB Connection

In some applications you have to debug and trace targets without physical access to the Debug/Trace interfaces, e.g. if the target is located in a closed chassis. TRACE32 ® supports several silicon IP solutions that enable full debug and trace functionality without limitations by using a USB connection between the target and your (host) computer. These solutions provide low-level access to the target without requiring physical access to Debug/Trace interfaces.

BENEFITS

Exploit Complete Debug Functionality without Dedicated Debug Port

USB debugging with TRACE32® offers you numerous advantages. While USB can be used to debug applications where traditional JTAG debugging cannot be used for various reasons, there are no limitations or differences in terms of functionality and user experience compared to our hardware-based products.

Debug and trace targets in a closed chassis

While debugging via JTAG requires direct access to the PCB, USB ports are usually accessible from outside the target case. TRACE32® allows you to use this USB connection for debugging and tracing. This is especially beneficial for in-field debugging and field returns.

Enabling smaller form factors of your device

By using the USB interface, you do not need an extra debug connector on your target’s PCB. This makes these solutions especially suitable for devices with tight board size requirements like consumer electronics in a small form factor.

Enable fast tracing

USB provides very high bandwidths in its latest generations. TRACE32® allows you to utilize the high data transfer rate for trace.

Full feature set and seamless integration

Our USB solution is based on the TRACE32® software stack for traditional JTAG debugging. Therefore you benefit from the full TRACE32® feature set, the same user interface and almost the same behavior that you know from our hardware debuggers. New TRACE32® features implemented in future releases are and will be always compatible between USB and JTAG versions.

SUPPORTED TECHNOLOGIES

TRACE32 ® Supports Various Technologies for Debug and Trace via USB

In the debug over USB scenario, TRACE32® is communicating with a special, silicon vendor-specific IP on the target system. This IP receives specially encoded debug commands via USB and passes them on to cores and other IP blocks via a on-chip communication infrastructure.

The TRACE32® software implements two parts, a front end and a back end. The back end receives high-level commands from the front end. Afterwards, it translates these high-level commands into chip-specific low-level commands to debug the cores via the IP-block and the communication infrastructure.

Tessent Embedded Analytics

The Tessent Embedded Analytics Ecosystem provides several analytic modules for debug and trace. The communication is based on messages which are routed by a message engine. The Communicators allow to transmit their message via various physical interfaces - one of them is USB.

Features

  • Full support for all IP blocks needed for debugging and tracing
  • Stop-mode debugging via USB stack
  • Multi-core debugging of identical cores and cores of different architectures
  • OS-aware debugging including Linux
  • Core trace and bus monitoring via USB stack

Interfaces Supported

USB

Supported Architectures

RISC-V
Xtensa
Arm Cortex
lauterbach-tessent-usb-debugging-overview

Intel Direct Connect Interface (DCI) DbC

Intel DCI DbC allows to debug Intel x86-Platforms via the USB port. The communication infrastructure is based on JTAG. The central component is the DCI bridge which generates JTAG scans based on the commands coming in via USB. These JTAG sequences allow you to access the internal Test Access Port (TAP) of the chip as well as externally connected JTAG devices (e.g., the CPU of a client or server system).

Features

  • Stop-mode debugging via USB stack
  • Multi-core debugging of identical cores (including hyperthreading) and cores of different architectures
  • BIOS/UEFI debugging with tailor-made GUI for all UEFI phases
  • Linux- and Windows-aware debugging

Interfaces Supported

USB

Supported Architectures

Intel x86
ARC
M8051EW
Xtensa
lauterbach-intel-dci-debugging-overview

Arm CoreSight Wire Protocol (CSWP)

The Arm CSWP protocol is a standardized transport protocol, which is agnostic of the physical link. By implementing Arms CoreSight SoC-600 IP the SoC can leverage access standards to debug memory space and an enhanced embedded trace router (ETR) that supports high-bandwidth streaming trace mode. Communication between the SoC and PowerView is controlled by a CSWP server implemented on the chip.

Features

  • Full support for all IP blocks needed for debugging and tracing
  • Stop-mode debugging via USB stack
  • Multi-core debugging of identical cores and cores of different architectures
  • OS-aware debugging including Linux
  • Core trace via USB stack

Interfaces Supported

USB

Supported Architectures

Arm
TYPICAL CONFIGURATIONS

Typical TRACE32 Configurations

PowerView_Software

Tessent Embedded Analytics for 64-bit RISC-V

Debug & Trace your SoC that is equipped with the USB Communicator of the Tessent Embedded Analytics IP.

PowerView_Software

Intel DCI DbC for Intel x86 Architecture

Debug & Trace your SoC that is equipped with the Intel Direct Connect Interface (DCI).

Section
Overview
Benefits
Supported Technologies
Typical Configurations

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