Xtensa Debugger & Trace

OVERVIEW

Any Xtensa Core in Any Chip

Xtensa is a configurable processor IP from Cadence which System Designers can optimize for their embedded application by sizing and selecting features and adding new instructions. Using our world-leading TRACE32® tools you can simultaneously debug and control a wide variety of Xtensa cores (along with all of the other cores) in an SoC via a single debug interface. TRACE32® supports all levels of application; form small embedded controllers up to large multi-core compute-intensive data-processing engines.

Supported Sub-Architectures

Xtensa LX4/LX5/LX6/LX7, Xtensa NX

DEBUG HIGHLIGHTS

Utilizing All Debug Features

Explore and utilize all the powerful and well-known features of your Xtensa core with Lauterbach debug modules: full on-chip breakpoint support; flash programming; benchmark counters; and cache view. And of course, everything is scriptable, enabling you to repeat the same test-sequence over and over.

Learn more about our debug system

Support of any Debug Interface Protocol

Debug via classic JTAG, compact JTAG (2-wire), Arm CoreSight SoC-400/600 (SWD, APB, JTAG-AP) and USB (Tessent).

Debug both Xtensa LX and NX processor architectures

Debug all versions of both Xtensa processor architectures using the same TRACE32® tools and debug feature set.

Debug Xtensa Cores in Multi-Architecture SoCs

Debug all your Xtensa cores and non-Xtensa cores at the same time with just one debug probe. Regardless of whether your multicore SoC architecture implements SMP or AMP.

Debug the full Software Stack

Work with many popular target operating systems like FreeRTOS™, ThreadX, the Android-based XOS and others. TRACE32® OS-aware debugging can query and display all OS objects such as threads, message queues and more.

Which Xtensa core do you want to use?
Check out our catalogue of predefined solutions and find the ideal toolset for your project.

Locate your chip

TRACE FEATURES

Capture Your Core’s Actions

Stop mode debugging can be a powerful tool but tracing is even better. Our Xtensa trace solutions support both the NEXUS-5001 compatible TRace Analyzer for Xtensa (TRAX) and off-chip tracing. TRAX is license free and stores the generated trace information to a user-configurable on-chip memory buffer. The off-chip trace solution provides significantly greater data gathering capabilities (up to 8GBytes) and support the embedding of TRAX packets in an Arm CoreSight trace stream. Used in the manner, trace correlation between cores can be performed.

Learn more about our trace system

Stream Trace Data at Ultra-High-Speed

Xtensa program flow trace can be spooled off-chip via a dedicated trace port, such as one using the Aurora Trace Protocol to a high-speed serial trace port. Our PowerTrace tools can then stream this trace data to a host at up to 400 MB/s.

Support of TRAX On-Chip Trace

The TRAX on-chip memory buffer is of limited size but it allows the identification of specific errors appearing only during run-time, like the source of an exception. It requires no additional trace license.

Analyse Interactions between Multiples Cores

Collect data from multiple cores simultaneously with multicore tracing. Record and analyze the dynamic interaction between cores. For mixed-architectures SoCs, we support protocols like CoreSight, to concurrently trace Xtensa and non-Xtensa cores.

Obtain detailed runtime information

Our trace solutions can record the complete program flow, provided by the SoCs trace IP. Using recorded data, detailed analyses are possible such as runtime analysis, cycle accurate timing*, and code-coverage measurements.

*Timestamps have to be configured within the Xtensa core.

Which Xtensa core do you want to use?
Check out our catalogue of predefined solutions and find the ideal toolset for your project.

Locate your chip

VIRTUAL PROTOTYPING

Get Ready Before Your Silicon is

Test your Xtensa code in your custom SoC before your SoC is ready. Taping out your SoC takes a lot of time but TRACE32 allows you to start software development on virtual prototypes and simulators, using the same GUI and toolset that you would use later with the real chip.

Verify your SoC, including debug mechanisms, before taping out, using simulated Verilog or VHDL netlists. The Lauterbach Generic Transactor Library (GTL) allows you to perform pre-silicon debugging at register level.

TOOLCHAIN SUPPORT

3rd Party Tools Supported for Xtensa

Target OS (4)

Product

Company

FreeRTOS

freeRTOS

Linux

ThreadX

Eclipse Foundation, Inc

XOS

Cadence Design Systems, Inc.

The following features are available for all architectures supported by TRACE32. Please contact us if your device or tool is not listed here; support is often already on its way.